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Prof. B.K. Mohanty
Prof. B.K. Mohanty
Head of Faculty
 
Education
: M.Sc (Physics), Ph.D. from Berhampur University, Orissa  
E-mail : bk.mohanti[AT]juet.ac.in  
Contact No. : Ext. - 315  
 
 
 
 
 
Areas of Interest: DSP & VLSI Array Processing.
   
Brief Background:
 
Received B.Sc and M.Sc degree (both with first-class honors) in Physics from Sambalpur University, Orissa, in 1987 and 1989, respectively. Received Ph.D degree in the area of VLSI for Digital Signal Processing from Berhampur University, Orissa in 2000.

In 1992 he was selected by OPSC (Orissa Public Service Commission) and joined as faculty member in the Department of Physics, SKCG College (Autonomous) Paralakhemundi, Orissa. In 2001 he joined as Lecturer in EEE Department, BITS Pilani, Rajasthan. Then he joined as an Assistant Professor in the Department of ECE, Mody Institute of Education Research (Deemed University), Rajasthan. In 2003 he joined Jaypee University of Engineering and Technology, Guna, Madhya Pradesh, where he becomes Associate Professor in 2005 and full Professor in 2007.

Currently he serves as the reviewers of IEEE Transactions on Circuits and Systems-II: Express Briefs, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. IET Circuit Device and Technology and Journal of Circuit, System and Signal Processing, Springer. He has member of various technical committees of International Conferences Sponsored by IEEE. Track Chair of “Multimedia Signal Processing Track”, International Symposium on Consumer Electronics (ISCE2011), Singapore and “Digital System Design and Validation Track” track of International Symposium of Electronics System Design (ISED2011), Kochi, India.

Rashtriya Gaurav Award for Meritorious Service, Outstanding Performance and Remarkable Role
 

Publication@JUET

Selected Journal Publication

1. B.K.Mohanty, G. Singh, and G. Panda, “Hardware design for VLSI implementation of FxLMS and FsLMS based active noise controllers”, Circuits Systems and Signal Processing, Regular Papers, (Accepted)

2. B.K.Mohanty, P.K.Meher and S. K. Patel, “LUT optimization for distributed arithmetic based block least mean square adaptive filter”, IEEE Transaction on Very Large Scale Integration Systems, Regular Papers, DOI:10.1109/TVLSI.2015.2472964. (On-line Available: IEEE Explore)

3. B.K.Mohanty, P.K.Meher, S.K.Singhal, and M.N.S.Swamy, “A High-Performance VLSI Architecture for Reconfigurable FIR using Distributed Arithmetic”, Journal of VLSI Integration, Elsevier, Vol.54, pp. 37-46, DOI.10.1016/j.vlsi.2016.01.006, June 2016, SCI

4. S.K.Singhal and B.K.Mohanty “Efficient parallel architecture for fixed-coefficient and variable-coefficient FIR filters using distributed arithmetic”, Journal of Circuits, Systems, and Computers (JCSC), DOI.10.1142/S0218126616500730, March 2016, SCI (on-line available)

5. B.K.Mohanty and P.K.Meher, “A high-performance FIR filter architecture for fixed and reconfigurable applications”, IEEE Transaction on VLSI Systems. Vol. 24, No.2, pp. 444-452, Feb. 2016, SNIP: 2.139, SJR: 0.624, Impact Factor: 1.89, H- Index: 69.

6. P.K.Meher, B.K.Mohanty, S. Patel, S.Ganguly and T. Srikanthan, “Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, vol.62, no.12, pp.2836-2845, Dec.2015. SNIP: 2.139, SJR: 1.41, Impact Factor: 3.56, H- Index: 68.

7. B.K.Mohanty and S.K.Singhal, “Area-delay and energy-efficient architecture for VLSI implementation of SDR channnelizer”, Circuit, Systems and Signal Processing, DOI 10.1007/s00034-015-0183-5, pp.1-14, October, 2015, SNIP: 0.982, SJR: 0.45, Impact Factor: 1.88, H-Index: 28, SCI

8. B.K.Mohanty and S. K. Patel, “Efficient very large scale integration architecture for variable length block least mean square adaptive filter”, IET Signal Processing,. DOI:10.1049/iet-spr.2014.0424, ISSN 1751-9683, Vol.9, No.8, pp.605-610, October 2015

9. H.Rabah, A. Amira, B.K.Mohanty, S. Maadeed, and P. K.Meher, “FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction, IEEE Transaction on VLSI Systems, Vol. 62, No.1, pp. 2209-2220, Oct. 2015, Oct. 2014, SNIP: 2.139, SJR: 0.624, Impact Factor: 1.89, H- Index: 69.

10. B.K.Mohanty, “Novel block formulation and area-delay-efficient reconfigurable interpolation FIR filter architecture for multi-standard SDR applications”, IEEE Transaction on Circuits and Systems-1, Regular Papers. Vol. 62, No.1, pp.283-291, Jan. 2015. SNIP: 2.139, SJR: 1.41, Impact Factor: 3.56, H- Index: 68.

11. B.K.Mohanty and Vikas Tiwari, “Modified probabilistic estimation bias formulation for hardware efficient fixed-width Booth multiplier”, Circuit, Systems and Signal Processing, Springer, July 2014, ISSN: 0278081X, DOI 10.1007/s00034-014-9843-0 SNIP: 0.982, SJR: 0.45, Impact Factor: 1.88, H-Index: 28.

12. B.K.Mohanty and S. K. Patel, “Area-delay-power efficient carry select adder”, IEEE Transaction on Circuits and Systems-II, Express Brief, ISSN: 15497747, Vol.61, No.6, pp.418-422, Jun. 2014, SNIP: 1.702, SJR: 0.932, Impact Factor: 1.92, H-Index: 53.

13. B.K.Mohanty and P.K.Meher, “Area-delay-power-efficient high-performance architecture for 2-D DWT using multiple lifting Scheme”, IET Image Processing, pp.1-8, May 2014, ISSN: 17519659, SNIP: 1.690, SJR: 0.32, Impact Factor: 1.16, H- Index: 16.

14. P.K.Meher, S.Y.Park, B,K.Mohanty, L.K.Seong and Y. C. Hao, “Efficient integer DCT architecture for HEVC”, IEEE Transaction on Circuits and Systems for Video Technology, Vol.24, No.1, pp.168-178, Jan. 2014, SNIP: 3.054, SJR: 1.45, Impact Factor: 4.58, H- Index: 124.

15. B.K.Mohanty, P.K.Meher, S.A.Madeed, and A.Amira, “Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN: 15498328, Vol.61, No.1, pp.120-133, Jan. 2014, SNIP: 2.139, SJR: 1.41, Impact Factor: 3.56, H- Index: 68.

16. B.K.Mohanty and Anurag Mahajan, “Scheduling Scheme and parallel architecture for computation of multilevel lifting 2-D DWT without using frame-buffer”, IET, Circuit, Device and Systems, ISSN: 1751858X, Vol.7, No.6, pp.319-325, Dec. 2013, SNIP: 0.882, SJR: 0.41, Impact Factor: 1.47, H- Index: 32.

17. B.K.Mohanty and Anurag Mahajan, “Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT”, ASP Journal of Low-power Electronics, Vol.9, No.1, pp.1-8, April 2013, ISSN: 15461998, SNIP: 0.388, SJR: 0.21, Impact Factor: 0.62, H- Index: 11.

18. B.K.Mohanty and P.K.Meher, Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT”, IEEE Transaction on Circuit and System for Video Technology, Vol.23, No.2, pp.353-363, Feb.2013. ISSN: 10518215, SNIP: 3.878, SJR: 2.82, Impact Factor: 4.45, H-Index: 162.

19. B.K.Mohanty and P.K.Meher, “A high-performance architecture for FIR adaptive filter based on a new distributed-arithmetic formulation of block least mean square algorithm”, IEEE Transaction on Signal Processing, Vol.61, no.4, pp. 921-932, Feb. 2013. ISSN: 1053587X, SNIP: 3.878, SJR: 2.82, Impact Factor: 4.45, H-Index: 162.

20. G.S.Maharana, P.K.Meher and B,K.Mohanty, “Efficient systolic architecture for VLSI realization of Heartly-like transforms”, International Journal of Computers and Application, ISSN:0975-8887, Vol.35, No.1, pp.1-7, Feb. 2013, ISSN: 1206212X, SNIP: 0.240, SJR: 0.14, Impact Factor:0.13,H- Index: 9.

21. B.K.Mohanty, Anurag Mahajan and P.K.Meher, “Area-power-efficient high-throughput implementation of lifting 2-D DWT”, IEEE Transaction on Circuit and System-II, Express Brief. Vol.59, no.7, pp.434-438, July 2012, ISSN: 15497747, SNIP: 1.702, SJR: 0.932, Impact Factor: 1.92, H-Index: 53.

22. B.K.Mohanty and P.K.Meher, Memory-efficient architecture for 3-D DWT using overlapped grouping of frames, IEEE Transaction on Signal Processing, Vol.59, No.11, pp. 5605-5616, Nov 2011, ISSN: 1053587X, SNIP: 3.878, SJR: 2.82, Impact Factor: 4.45, H-Index: 162.

23. B.K.Mohanty and P.K.Meher, “Memory-efficient modular VLSI architecture for high-throughput and low-latency implementation of multilevel lifting 2-D DWT, IEEE Transaction on Signal Processing, Vol.59, No.5, pp.2072-2084, May 2011, ISSN: 1053587X, SNIP: 3.878, SJR: 2.82, Impact Factor: 4.45, H-Index: 162.

24. B.K.Mohanty and P.K.Meher, “Parallel and pipeline architecture for high-throughput computation of 3-D DWT, Regular Paper, IEEE Transaction on Circuit and System for Video Technology, Vol.20, No.9, pp.1200-1209, Sept. 2010. ISSN: 10518215, SNIP: 3.054, SJR: 1.45, Impact Factor: 4.58, H- Index: 124.

25. P.K.Meher, B.K.Mohanty and J.C.Patra, “Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform”, IEEE Transaction on Circuit and System -II, Express Briefs, Vol.55, No.2, pp.151-154, Feb. 2008, ISSN: 15497747, SNIP: 1.702, SJR: 0.932, Impact Factor: 1.92, H-Index: 53.

26. B.K.Mohanty and P.K.Meher: “High-throughput and low-latency implementation of bit-level systolic architecture for 1-D and 2-D digital filters”, IET Computer and Digital Technique, Vol. 146, No. 2, pp. 91-99, March 1999. ISSN: 17518601, (Impact factor: 0.284, SNIP:0.699, SJR:0.270).

27. B.K.Mohanty and P.K.Meher: “Novel flexible systolic mess architecture for parallel VLSI implementation of finite digital convolution”, IETE Journal of Research, Vol. 44, No.6, pp.261-266 Nov. 1998. ISSN: 03772063, (Impact factor: 0.2, SNIP:0.504, SJR: 0.169).

28. B.K.Mohanty and P.K.Meher: “Cost-effective novel flexible cell-level systolic architecture for high-throughput implementation of 2-D FIR filter”, IET Computer and Digital Technique, Vol. 143, No.6, pp.436-439, Nov. 1996, ISSN: 17518601, Impact factor: 0.284

Selected Conference Publication

1. B.K.Mohanty, Vivek Chaturvedi, Vijeta Rathore, and T.Srikanthan, “Memory-Access Aware Work-Load Distribution for Peak-Temperature Reduction of 3D Multi-core Embedded Systems”, IEEE International Conference on Digital Signal Processing, Singapore, July 2015, pp.1270-1277. (IEEE Explore)

2. Vivek Chaturvedi, B.K.Mohanty, and T.Srikanthan, “Leakage-Aware Intra-Task Dynamic Voltage Scaling Technique for Energy Reduction in Real-Time Embedded Systems”, IEEE International Conference on Digital Signal Processing, Singapore, July 2015, pp.1266-1269. (IEEE Explore)

3. Carlo Safarian, T.Ogunfunmi, W.J.Kojacky and B.K.Mohanty, “FPGA implementation of LMS-based FIR adaptive filter for real-time digital signal processing applications”, IEEE International Conference on Digital Signal Processing, Singapore, July 2015, pp.1251-1254. (IEEE Explore)

4. B.K.Mohanty, P.K.Meher, and T. Srikanthan, “Critical-path optimization for efficient hardware realization of lifting and flipping DWTs”, IEEE International Symposium on Circuits and Systems (ISCAS-2015), pp.1186-1189, May 2015, Portugal,.

5. B.K.Mohanty, P.K.Meher and M.N.S.Swamy, “Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT using 9/7 and 5/3 Filters, 28 International Conference on VLSI Design, (VLSI-2015), pp.527-533, Bangaluru, India, 3-7 January 2015.

6. P.K.Meher, B.K.Mohanty and T. Srikanthan, “Area-Delay Efficient Architecture for MP Algorithm Using Reconfigurable Inner-Product Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS-2014), pp.2628-2631, May 2014, Australia.

7. B.K.Mohanty, S.A.Madeed, and A.Amira, “Systolic architecture for hardware efficient implementation of 2-D non-separable filter bank, In.Proc. International Design and Testing Symposium, Doha, Qatar, Dec.2012.

8. B.K.Mohanty, P.K.Meher and Subodh Singhal, “Efficient architectures for implementation of 2-D discrete Hadamard transform”, In Prco. IEEE International Symposium on Circuits and Systems, ISCAS 2012, pp.1480-1483, Seoul, South Korea, May 2012.

9. Anurag Mahajan and B.K.Mohanty, Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic, In Proc. IEEE Asia Pacific Conference on Circuit and Systems, APCCAS-2010, pp. 1195-1198, Malaysia, Dec 5-9, 2010

10. B. K.Mohanty and P.K.Meher, “Efficient multiplier-less design for 1-D DWT using 9/7 filters based on distributed arithmetic,” IEEE International Symposium on Integrated Circuits (ISIC-2009), pp.364-367, 14-15 Dec, Singapore, 2009.

11. B. K.Mohanty and P.K.Meher , “DA based bit-serial systolic architecture for 2-D non-separable discrete wavelet transform,” IEEE International Symposium on Integrated Circuits (ISIC-2009), pp.159-162, 14-15 Dec, Singapore, 2009

12. B.K.Mohanty and P.K.Meher, “New scan method and pipeline architecture for VLSI implementation of separable 2-D FIR filters without using transposition,” IEEE Region 10 TENCON2008 Conference, Hyderabad, 2008

13. B.K.Mohanty and P.K.Meher, “Delayed block LMS algorithm and concurrent architecture for high-speed implementation of adaptive FIR filters,” IEEE Region 10 TENCON2008 Conference, Hyderabad, Nov. 2008.

14. B.K.Mohanty and P.K.Meher, “Concurrent systolic architecture for high-throughput implementation of 3-Dimensional discrete wavelet transform”, 19th IEEE International Conference Application-specific Systems, Architectures and Processors, ASAP'08, pp. 168-172, Belgium, 2008

15. B.K.Mohanty and P.K.Meher , “Throughput-Scalable Hybrid-Pipelined architecture for multilevel lifting 2-D DWT of JPEG 2000 Coder”, 19th IEEE International Conference Application-specific Systems, Architectures and Processors, ASAP'08, pp. 311-315, Belgium, July 2008

16. B. K. Mohanty and P. K. Meher “Memory-Efficient DA-Based Systolic Architecture for High-Speed Implementation of FIR Filters, IEEE International Workshop on Digital infoTainment and Visualization, IWDTV'08, Singapore, June 2008

17. B.K.Mohanty and Anurag Mahajan “CSE and CSD based systolic design for low-complexity VLSI implementation of 1-D DWT”, National Conference on Communication System and Networking, CSN-08, JIET, Guna, 2008.

18. B. K.Mohanty and P.K.Meher, Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform, IEEE International Conference on Intelligent and Advanced Systems (ICIAS-2007), pp.1355-1358, Malaysia. May 2007.

19. B.K.Mohanty and P.K.Meher, “Pipelined architecture for high-speed implementation of multilevel lifting 2-D DWT using 9/7 filters, IEEE International Symposium on Signal Circuit and Systems, ISSCS2007, pp.137-140, July, Romania, July 2007.

20. B.K.Mohanty and P.K.Meher, “Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform” IEEE Asia Pacific Conference on Circuit and Systems, APCCAS-2006, pp.462-465, Singapore, 2006

21. B.K.Mohanty and P.K.Meher “VLSI Architecture for High-Speed/Low-Power Implementation of Multilevel Lifting DWT” IEEE Asia Pacific Conference on Circuit and Systems APCCAS-2006, pp. 458-461, Singapore, 2006

22. B.K.Mohanty and P.K.Meher “Bi-layer systolic architecture for bit-serial implementation of Discrete Wavelet Transform”, 10th IEEE International Conference on Communication Systems ICCS 2006, Singapore, 2006

23. B.K.Mohanty and P.K.Meher, “Systolic architecture for transposition free VLSI implementation of 2-D DWT”, 10th IEEE International Conference on Communication Systems ICCS 2006, Singapore, 2006.

24. B.K.Mohanty: “Recursive Relation and Systolic Architecture for VLSI Implantation of Digit Serial Multiplier”, In Proc. Third National Conference on Applicable Mathematics in Wave Mechanics and Vibrations (WMVC-2006), Oct. 2006, Guna.

25. B.K.Mohanty: “Improved systolic architecture for non-separable two-dimensional discrete wavelet transform”, Accepted at World Informatika Conference, WEC’05 in Prague, Czech Republic, August 26-2, 2005.

26. B.K.Mohanty: “Digit-serial architectures for VLSI implementation of DLMS adaptive FIR filters ”, Accepted at WSEAS 2004 Conferences in Salzburg, AUSTRIA, February 13-15, 2004

27. B.K.Mohanty and P.K.Meher: “Systolic arrays for high-speed implementation of IIR Digital filters”, Accepted at IASTED International Conference on Signal and Image Processing, SIP’98, USA.

28. B.K.Mohanty and P.K.Meher: “Systolic architecture for massively parallel implementation FIR and Linear phase FIR filters”, Accepted at IASTED International Conference on Signal and Image Processing Applications, SIPA’96, France

 

 

 

 

 

 

 

       
 
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