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Dr. Jitendra Kanungo
Dr. Jitendra Kanungo
Assistant Professor(SG)
 
Education
: M. Tech., Ph.D. (IIT Roorkee)  
E-mail : jitendra.kanungo[AT]juet.ac.in  
Contact No. : Ext. - 123  
 
 
 
 
 
Areas of Interest: Ultra low power digital circuit design, circuit/device co-design issues.
   
Brief Profile:
 
Dr. Jitendra Kanungo has completed Ph.D. in the area of Ultra Low Power VLSI Circuit Design from Department of Electronics & Communication Engineering, Indian Institute of Technology (IIT) Roorkee in year 2013. He has received M. Tech. (Micro-electronics) degree from University Centre for Instrumentation & Microelectronics (UCIM), Panjab University Chandigarh in year 2003 and M.Sc. (Electronics) degree from School of Electronics (SOE), Devi Ahilya University Indore in year 2001. During August 2004 to July 2007, he was a lecturer (ECE) in the College of Engineering Roorkee (COER) India.

During July 2007 to July 2008, he has worked as Research Fellow in the project SMDP-II at the Department of Electronics & Computer Engineering, IIT Roorkee. This project was governed by the Ministry of Communication & Information Technology (MCIT), Govt. of India. He has published six research papers in peer reviewed journals and international conferences during his Ph.D. tenure at IIT Roorkee.

Ph. D. Supervision

Research Scholar Status

1. Mr. Durgesh Nandan : Awarded(Oct.2018)
2. Mr. Dharmendra Jain : Submitted
3. Mr. Beerendra Kumar Patel : Ongoing

M. Tech. Supervision

1. Trapti Mudgal (2016)
2. Mr. Beerendra Kumar Patel (2015)

Reviewer of International Journals:

1. IET, Circuits, Devices and Systems
2. Springer Journal of Circuits, Systems and Signal
3. Journal of Institution of Engineers (India)- Series B
4. JUET Research Journal of Science & Technology
5. Journal of Microelectronics and Solid State Electronics, Scientific & Academic Publishing (SAP), USA.

 

Publication@JUET

Publication details google profile link

1. Durgesh Nandan, Mahajan A., and Kanungo, J. “An efficient VLSI architecture design of antilogarithm converter with 10-regions error correction scheme,” Journal of Mathematical Modelling of Engineering Problems, International Information and Engineering Technology Association (IIETA), 2021 (In press).

2. Dharmendra Jain, Jitendra Kanungo, and S. K. Tripathi, “Enhancement in Performance of Supercapacitor using Eucalyptus Leaves Derived Activated Carbon Electrode with CH 3 COONa and HQ Electrolytes: Step towards Environment Benign Supercapacitor” Journal of Alloys and Compounds, vol. 832, pp. 1-6, 2020.

3. D. Jain, J. Kanungo, and S. K. Tripathi, "Performance enhancement approach for supercapacitor by using mango kernels derived activated carbon electrode with p-hydroxyaniline based redox additive electrolyte", Materials Chemistry and Physics, vol. 229, pp. 66-77, May, 2019.

4. D. Jain, J. Kanungo, and S. K. Tripathi, "Characterization of Supercapacitor for the Development of Energy Storage Units", International Conference on Signal Processing and Communication (ICSC- 2019) organized from March 07-09, 2019 at JIIT, Noida.

5. Dharmendra Jain, Jitendra Kanungo and S. K. Tripathi, "Enhanced performance of ultra-capacitors using redox additive based electrolytes", Applied Physics A, vol. 124, pp.397, May 2018.

6. Durgesh Nandan, Kanungo, J. and Mahajan, A., "An errorless Gaussian filter for image processing by using expanded operand decomposition logarithm multiplication," Springer, Journal of ambient intelligence and humanized computing, 2018.

7. Durgesh Nandan, Kanungo, J. and Mahajan A., "An efficient VLSI architecture design of Leading One Detector," International journal of pure and applied mathematics, vol. 118, no. 14, pp. 267-272, 2018.

8. Durgesh Nandan, Kanungo, J. and Mahajan A., "An efficient architecture of Iterative Logarithmic Multiplier," International journal of engineering & technology (UAE), vol. 7, no. 2.16, pp. 24-28, 2018.

9. Durgesh Nandan, Jitendra Kanungo and Anurag Mahajan "An Efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition," Elsevier, VLSI the integration journal, Vol. 58, pp. 134-141, June 2017.

10. Durgesh Nandan, Jitendra Kanungo and Anurag Mahajan, "An efficient VLSI architecture for Iterative Logarithmic Multiplier,” IEEE 4th International conference on signal processing and integrated networks (SPIN), Noida, pp.419-423, Feb.2017.

11. Durgesh Nandan, Jitendra Kanungo and Anurag Mahajan, "An Efficient VLSI architecture design for antilogarithmic converter by using the error correction scheme," IETE International conference on signal processing (ICSP), SATI, Vidisha, 11-13 Nov. 2016.

12. Jitendra Kanungo and S. Dasgupta, "Analysis of Energy-Efficient Single Phase Adiabatic Logic at Sub-100 nm CMOS Technology," JUET Research Journal of Science & Technology, vol. 2, no. 1, pp. 133- 138, Jan. 2015.

13. Jitendra Kanungo and S. Dasgupta, "Sinusoidal Clocked Sense-Amplifier Based Energy Recovery Flip-Flops," World Scientific Journal of Circuits, Systems and Computers, vol. 23, no. 5, pp. 1450066-1-1450066-19, March 2014.

14. Jitendra Kanungo and S. Dasgupta, "Performance Analysis of a Complete Adiabatic System Driven by the Proposed Power Clock Generator." IOP Science, Journal of Semiconductors, vol. 35, no. 9, pp. 095001-1- 095001-7, Sep. 2014.

15. Jitendra Kanungo and S. Dasgupta, "Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach," IOP Science, Journal of Semiconductors, vol. 34, no. 8, pp. 085001-1- 085001-5, Aug. 2013.

 

 

 

 

 

 

 

       
 
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