Dr. Subodh Kumar Singhal

Dr. Subodh Kumar Singhal – JUET, Guna

Academic Position

• Assistant Professor (SG) in the Department of Electronics & Communication Engineering at JUET, Guna.
• Joined JUET in 2007, prior to which he served as a Research Engineer at MANIT, Bhopal (2006–2007).
• Holds over 18 years of teaching experience.

Educational Background

• B.E. in Electronics & Communication Engineering, obtained in 2004 from R.G.P.V, Bhopal.
• M.Tech in VLSI Design, from Atal Bihari Vajpayee IIITM, Gwalior (2006).
• Ph.D., completed at JUET, Guna in 2017, in the area of VLSI implementation of DSP algorithms.

Research Interests & Contributions

• His notable research areas include:
• VLSI architecture design
• ASIC and FPGA implementations
• Digital Signal Processing (DSP) algorithms
• Image Processing
• He is also active as a reviewer for journals like various IEEE Transactions, Journal of Circuit, Systems and Signal Processing, and Springer publications.
• Fellow member of  IETE.

Publications & Scholarly Impact

• Published 13+ technical papers including 7 SCI.
• Published one Book, one book chapter.
• Granted 3 patents.
• Over 80 citations, and his involvement in technical publications related to VLSI and DSP areas.

SCI/Scopus Journal Papers:

1. Paper titled,  “Efficient parallel architecture for fixed-coefficient and variable-coefficient FIR filters using distributed arithmetic”, Journal of Circuits, Systems, and Computers (JCSC), Vol. 25, No. 7, pp. 1650073-1-1650073-19, April 2016 (SCI)  (Co-author: B. K. Mohanty).

2.   Paper titled, “A High-Performance VLSI Architecture for Reconfigurable FIR using Distributed Arithmetic”, Journal of VLSI Integration, Elsevier, Vol. 54, pp. 37-46, June 2016 (SCI) (Co-authors: P. K. Meher, B. K. Mohanty, and M.N.S Swami).

3. Paper titled, “Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer”, Journal of Circuits, Systems, and Signal Processing, Springer, Vol. 35, No. 8, pp. 2958-2971, August 2016 (SCI) (Co-author: B. K. Mohanty).
4. Paper titled, “Area–delay and energy efficient multi-operand binary tree adder”, IET Circuits, Devices & Systems,  Vol. 14, No. 5, pp. 586-593, August 2020 (SCI) (Co-author: Sujit Kumar Patel).
5. Paper titled, “Efficient Diminished-1 Modulo (2ⁿ + 1)) Adder Using Parallel Prefix Adder”, Journal of Circuits, Systems, and Computers (JCSC), Vol. 29, No. 12, pp. 2050186, September 2020 (SCI) (Co-author: B. K. Mohanty, Sujit Kumar Patel, Gaurav Saxena).
6. Paper titled, “Area-delay efficient Radix-4 8× 8 Booth multiplier for DSP applications”, Turkish Journal of Electrical Engineering & Computer Sciences, Vol. 29, No. 4, pp. 2012-2028, July 2021 (SCI) (Co-author: Anurag Mahajan, Sujit Kumar Patel, Gaurav Saxena).
7. Paper titled, “An area-delay efficient single-precision floating-point multiplier for VLSI systems”, Journal of microprocessors and microsystems, Elsevier, Vol. 98, pp. 104798, Feb. 2023 (SCI) (Co-author: Sujit Kumar Patel, Anuradha).
8. Paper titled, “A Phase Modulation-Based Approach for Theft-Proof Electricity Distribution in India Using CDMA Technology” Journal Européen des Systèmes Automatisés, by International Information and Engineering Technology Association (IIETA) 57, no. 6 (2024): pp. 1687-1695. (Scopus Indexed) (Co-Authors: Gaurav Saxena, Snehil Bhosle, Prateek Pandey)
9. Paper titled, “An Efficient Method of Modulo Adder Design for Digital Signal Processing Applications”, Journal MethodsX. Elsevier Vol.14 (2025): pp. 103216. (Scopus Indexed) (Co-Authors: Gaurav Saxena, Sujit k. Patel, Sumit Kumar and k. Anjali Rao).

10. Paper titled, “An Efficient Reconfigurable Floating Point Multiplier Design for Signal Processing Applications”, Journal of Review of Computer Engineering Research (RCER), January 2026 (Accepted). (Co-Authors: Sujit kumar Patel, and Anurag Mahajan)

Others:

1. Paper titled, “Enhanced Image Protection Using Discrete Fractional Fourier Domain and Dual Random Phase Encoding”, New Horizons of Science, Technology and Culture, Vol.2 (2025): pp. 78-96. (Co-Authors: Deepak Sharma, Prateek Pandey).

2.   Paper titled, “Performance Analysis of Single Image Fog Expulsion Techniques” in proceeding of 2021 10th IEEE International Conference on Communication Systems and Network Technologies (CSNT), pp. 182-187, June 2021 (Co-authors: Gaurav Saxena, Sarita Singh Bhadauria).

3.    Paper titled, “Efficient Architectures for VLSI Implementation of 2-D Discrete Hadamard Transform,” IEEE International Symposium on Circuit and Systems (ISCAS-2012), May 20-23, Seoul, Korea (Co-authors: P. K. Meher, B. K. Mohanty).

4.    Paper titled, “Design of 1.5 GHz Quasilumped Microstrip Highpass Filter” in proceeding of International conference Computational Intelligence, Communication Systems and Networks, pp. 268-270, 23-25 July 2009 (Co-authors: Deepak Sharma, R.M.S. Dhariwal). 

5.    Paper titled, “Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited Stubs” in proceeding of International conference Computational Intelligence, Communication Systems and Networks, pp. 264-267, 23-25 July 2009 (Co-authors: Deepak Sharma, R.M.S. Dhariwal).

Patent/Design/Copyright

11. Published a design patent titled as “A JAW BASED MICROWAVE OVEN “, Design number: 469247-001, with Patent Office, Government of INDIA on 28/10/25.

22. Published a design patent titled as “HIGH PRESSURE CLEANING ROBOT “, Design number: 469245-001, with Patent Office, Government of INDIA on 02/01/26.

33. Published a design patent titled as “TERRAIN INSPECTION ROBOT “, Design number: 469244-001, with Patent Office, Government of INDIA on 02/02/26.

44. Published a design patent titled as “CARGO LIFTING ROBOT “, Design number: 469244-001, with Patent Office, Government of INDIA on 20/05/26

55. Published a design patent titled as “CHAIR “, Design number: 425689-001, with Patent Office, Government of INDIA on 19/11/24

66. Published a design patent titled as “SOWER STICK “, Design number: 425690-001, with Patent Office, Government of INDIA on 12/09/2024

77. Published a design patent titled as “SEGWAY SCOOTER “, Design number: 425687-001, with Patent Office, Government of INDIA on 19/09/2024