Dr. Jitendra Kanungo

    Ph.D. (IIT Roorkee)

   Senior Member IEEE

    Publications:

2025

1.      D. Sharma, Jitendra Kanungo, N. Singh, and J. Raghuwanshi, “A Comparative Review of Machine Learning and Computer Science Techniques for Optimising Healthcare Management Systems,” New Horizons of Science, Technology and Culture Vol. 4, pp. 15–32, 2025.

2.      Jitendra Kanungo, J. Raghuwanshi, D. Sharma, and S. Dasgupta, “Energy Efficient Single Phase Adiabatic Logic and Its Application in Ripple Carry Adder Design,” Circuits, Systems, and Signal Processing, pp. 1–17, 2025.

2024

3.      D. Sharma, N. Singh, Jitendra Kanungo, and J. Raghuwanshi, “A Novel Image Compression Technique with Multiple Parameter Discrete Fractional Fourier Transform for Satellite and Medical Imaging,” Science and Technology: Developments and Applications Vol. 1, pp. 96–135, 2024.

4.      D. Nandan, Jitendra Kanungo, and A. Mahajan, “An error-efficient Gaussian filter for image processing by using the expanded operand decomposition logarithm multiplication,” Journal of ambient intelligence and humanized computing, vol. 15, no. 1, pp. 1045–1052, 2024.

2023

5.      D. Jain, S. Tripathi, Jitendra Kanungo, and B. Gupta, “Fabrication and characterization of supercapacitor comprising mango kernel derived electrode under different electrolyte system,” Energy Storage, vol. 5, no. 3, p. e465, 2023.

 2022

6.      P. Beerendra and Jitendra Kanungo, “Design of an Efficient Reverse Converter for Moduli Sets 2 (4p)+ 1, 2 (p)+ 1, 2 (p)-1, 2 (2p)+ 1, 22p,” JOURNAL OF ENGINEERING RESEARCH, vol. 10, 2022.

7.      B. K. Patel and Jitendra Kanungo, “Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder,” Journal of Engg. Research ICAPIE Special Issue pp, vol. 8, p. 18, 2022.

 2021

8.      B. Patel and Jitendra Kanungo, “Efficient tree multiplier design by using modulo 2n+ 1 adder, in 2021 Emerging Trends in Industry 4.0 (ETI 4.0).” IEEE, 2021.

9.      P. Beerendra and Jitendra Kanungo, “Design of an Efficient Reverse Converter for Moduli Sets,”  Journal of Engg. Research, ICMET Special Issue, 2021.

2020

10.  D. Nandan, A. Mahajann, and Jitendra Kanungo, “An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme,” Journal of Mathematical Modelling of Engineering Problems, International Information and Engineering Technology Association (IIETA), vol. 8, no. 2, pp. 213–218, 2020.

11.  D. Jain, Jitendra Kanungo, and S. Tripathi, “Enhancement in performance of supercapacitor using eucalyptus leaves derived activated carbon electrode with CH3COONa and HQ electrolytes: A step towards environment benign supercapacitor,” Journal of Alloys and Compounds, vol. 832, p. 154956, 2020.

 2019

12.  D. Jain, Jitendra Kanungo, and S. Tripathi, “Synergistic approach with redox additive for the development of environment benign hybrid supercapacitor,” Journal of the Electrochemical Society, vol. 166, no. 14, p. A3168, 2019.

13.  D. Jain, Jitendra Kanungo, and S. Tripathi, “Performance enhancement approach for supercapacitor by using mango kernels derived activated carbon electrode with p-hydroxyaniline based redox additive electrolyte,” Materials Chemistry and Physics, vol. 229, pp. 66–77, 2019.

14.  D. Nandan, K. Kumar, Jitendra Kanungo, and R. K. Mishra, “Compact and errorless 16-region error correction scheme for antilogarithm converter,” in 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2019, pp. 1–5.

15.  D. Jain, Jitendra Kanungo, and S. K. Tripathi, “Characterization of supercapacitor for the development of energy storage units,” in 2019 International Conference on Signal Processing and Communication (ICSC), 2019, pp. 264–270.

2018

16.  D. Jain, Jitendra Kanungo, and S. Tripathi, “Enhanced performance of ultracapacitors using redox additive-based electrolytes,” Applied Physics A, vol. 124, no. 5, p. 397, 2018.

17.  D. Nandan, Jitendra Kanungo, and A. Mahajan, “An efficient architecture of iterative logarithm multiplier,” Int. J. Eng. Technol, vol. 7, no. 2.16, pp. 24–28, 2018.

18.  B. K. Patel and Jitendra Kanungo, “Diminished-1 multiplier using modulo adder,” International Journal of Engineering & Technology, vol. 7, no. 4.20, pp. 31–35, 2018.

19.  D. Nandan, Jitendra Kanungo, and A. Mahajan, “65 years journey of logarithm multiplier,” International journal of pure and applied mathematics, vol. 118, no. 14, pp. 261–266, 2018.

2017

20.  D. Nandan, Jitendra Kanungo, and A. Mahajan, “Implementation of Leading One Detector based on reversible logic for logarithmic arithmetic,” International Journal of Computer Applications, vol. 173, no. 8, pp. 40–45, 2017.

21.  D. Nandan, A. Mahajan, and Jitendra Kanungo, “An efficient antilogarithmic converter by using 11-regions error correction scheme,” in proc. 2017 4th international conference on signal processing, computing and control (ISPCC), 2017, pp. 118–121.

22.  Durgesh Nandan, Jitendra Kanungo and Anurag Mahajan, “An efficient VLSI architecture for Iterative Logarithmic Multiplier,” IEEE 4th International conference on Signal Processing and Integrated Networks (SPIN), Noida, pp.419-423, Feb.2017.

2016

23.  D. Nandan, Jitendra Kanungo, and A. Mahajan, “An Efficient VLSI architecture design for antilogarithmic converter by using the error correction scheme,” in ​proc. International Conference on Signal Processing​​ (ICSP 2016), 2016, pp. 1–5.

 2015

24.  Jitendra Kanungo and S. Dasgupta, “Analysis of Energy-Efficient Single Phase Adiabatic Logic at Sub-100 nm CMOS Technology,” JUET Research Journal of Science & Technology, vol. 2, no. 1, pp. 133–138, 2015.

25.  H. Sharma, S. Tomar, and Jitendra Kanungo, “FPGA implementation of 4-bit parallel Cyclic Redundancy Code,” International Journal of Research in Engineering and Technology, vol. 4, no. 11, pp. 111–113, 2015.

 2014

26.  Jitendra Kanungo and S. Dasgupta, “Sinusoidal clocked sense-amplifier-based energy recovery flip-flops,” Journal of Circuits, Systems, and Computers, vol. 23, no. 05, p. 1450066, 2014.

27.  Jitendra Kanungo and S. Dasgupta, “Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator,” Journal of Semiconductors, vol. 35, no. 9, p. 095001, 2014.

 2013

28.  Jitendra Kanungo and S. Dasgupta, “Energy estimation for n-input adiabatic logic gate: A proposed analytical model,” Journal of Circuits, Systems and Computers, vol. 22, no. 05, p. 1350037, 2013.

29.  Jitendra Kanungo and S. Dasgupta, “Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach,” IOP Science, Journal of Semiconductors, vol. 8, no. 34, pp. 79–83, 2013.

30.  Jitendra Kanungo and S. Dasgupta, “Single Phase Energy Recovery Logic and Conventional CMOS Logic: A Comparative Analysis,” Journal of Microelectronics and Solid State Electronics, vol. 2, no. 2A, pp. 16–21, 2013.

31.  Jitendra Kanungo and S. Dasgupta, “Scaling trends in energy recovery logic: an analytical approach,” Journal of Semiconductors, vol. 34, no. 8, p. 085001, 2013.

 2012

32.  R. Kumbhare, Jitendra Kanungo, A. Saxena, and S. Dasgupta, “Design of an Ultra Low Power Clock Gating D Flip-Flop Using Quasi-Static Energy Recovery Logic,” Microelectronics and Solid State Electronics-Scientific & Academic Publishing, USA, vol. 1, no.1, pp. 9-14, 2012.

33.  Jitendra Kanungo and S. Dasgupta, “The Study of Energy Efficiency of Single Phase Energy Recovery Logic with Progressive Technology,” in Symposium on VLSI Design and Testing 2011 (VDAT-2011), 2011, pp. 1–10.

 2011

34.  Jitendra Kanungo and S. Dasgupta, “An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design,” Journal of Low Power Electronics, vol. 7, no. 3, pp. 381–392, 2011.

 2010

35.  Jitendra Kanungo and S. Dasgupta, “Key Challenges in Adiabatic Logic Circuits at sub-100 nm Scale,” in International conference on communication, computers and devices (ICCCD), IIT Kharagpur, 2010, pp. 1–4.

 2009

36.  Jitendra Kanungo, and S. Dasgupta, “Performance Analysis of 4 x 4 Array Multiplier Units using various Full Adder Cells at 70 nm Scale,” 15th International Workshop on The Physics of Semiconductor Devices (IWPSD), Delhi (India), December 15-19, 2009.

 2007

37.  Jitendra Kanungo, Joshi R.C., Dasgupta S. (2007): “FPGA Implementation of Dynamic Time Warping Algorithm for Recognition of Spoken words using VHDL,” National Conference on Emerging Trends in Information Technology (NCETIT-2007), SGSITS, Indore.

38.  Jitendra Kanungo, Dasgupta S., and Joshi R.C, “Performance analysis of various full adder cells at 70nm scale”, International Conference of Soft Computing and Intelligent Systems, Jabalpur Engineering College, Jabalpur, 27-29, Dec. 2007.

    Ph. D. Supervision: 

1. 1. Mr. Durgesh Nandan : Awarded
   2. Mr. Dharmendra Jain : Awarded 
   3. Mr. Beerendra Kumar Patel : Awarded